About Me
Hey there, I'm Swagat!
You can call me Swag! My journey has taken me through three unique "West" locations: West Bengal, West Virginia, and West Lafayette. Although I've spent countless hours as a lab rat, I like to think I'm a bit different from the usual, having extensive industrial experience. With a vibrant and fun-loving personality, I've always been driven by a deep passion for learning and exploration, instilled in me by incredible teachers and mentors back in my enchanting hometown of Morgantown, West Virginia.
My academic adventures led me to Purdue University, where I triple majored in Electrical Engineering, Applied Physics, and Mathematics. I then joined Georgia Tech as an NSF Graduate Research Fellow and completed an MS in Electrical Engineering. My MS thesis topic was neuromorphic circuits and systems. I am currently a Field Applications Engineer at Renesas Electronics America. When I'm not immersed in circuits and systems, I find joy in working out with friends, reading, and practicing Hindustani classical music (vocal and bamboo flute).
| Academic History | ||
|---|---|---|
| Institution | Degree | Year |
| Georgia Institute of Technology | MS in Electrical Engineering | 2024 |
| Purdue University -- Honors College | BS in Electrical Engineering | 2022 |
| BS in Applied Physics | 2022 | |
| BS in Mathematics | 2022 | |
| Morgantown High School | HS Diploma | 2018 |
Research
I build stuff.
My research is highly interdisciplinary, combining the areas of circuits, signal processing, controls, and computational neuroscience. I aim to create systems that can efficiently sense and process information like humans by utilizing bioinspired, asynchronous sensing and computing. An updated list of my published works can be found on Google Scholar. Here are public-domain releases of my work:
Patents
| 1) | Irazoqui P, Shah J, Meyer T, Ganesh V, Bhattacharyya S, & Hsiung Y, “Multimodal Seizure Sensing,” Published Nov 2023 |
Journals
| 1) | Bhattacharyya S & Hasler J, “A Six-Transistor Integrate-and-Fire Neuron Enabling Chaotic Dynamics,” IEEE Transactions on Biomedical Circuits and Systems, vol ##, no ##, ### 2025 |
| 2) | Mathews P, Ayyappan PR, Ige A, Bhattacharyya S, Yang L, & Hasler J, “A 65 nm CMOS Analog Programmable Standard Cell Library for Mixed-Signal Computing,” IEEE Transactions on VLSI Syst., vol 32, no 10, Oct 2024 |
| 3) | Bhattacharyya S & Hasler J, “Extrema-Triggered Conversion for Non-Stationary Signal Acquisition in Wireless Sensor Nodes,” JLPEA, vol 14, no 1, Feb 2024 |
| 4) | Bhattacharyya S, Ayyappan PR, & Hasler J, “Towards Scalable Digital Modeling of Networks of Biorealistic Silicon Neurons,” IEEE Journal on Emerging and Selected Topics in CAS, vol 13, no 4, pp 927-939, Dec 2023 |
| 5) | Bhattacharyya S & Graham DW, “Amplitude-Regulated Quadrature Sine-VCO Employing an OTA-C Topology,” IEEE Transactions on CAS II: Express Briefs, vol 70, no 6, pp 1886-1890, June 2023 |
| 6) | Bhattacharyya S, Andryzcik S, & Graham DW, “An Acoustic Vehicle Detector & Classifier Using a Reconfigurable Analog/Mixed-Signal Platform,” JLPEA, vol 10, no 1, Article 6, March-April, 2020 |
Conferences
| 1) | Mathews P, Ayyappan PR, Ige A, Bhattacharyya S, Yang L, & Hasler J, “A 65nm and 130nm CMOS program-mable analog standard cell library for scalable system synthesis,” IEEE CICC, Denver, CO, Apr 21-24, 2024 |
| 2) | Bhattacharyya S, Yang L, & Hasler J, “BuzzSort: A Linear-Time, Event-Driven Data Conversion and Sorting Framework for Approximate Computing Architectures,” IEEE ICRC, San Diego, CA, Dec 5-6, 2023 |
| 3) | Bhattacharyya S & Hasler J, “Extrema-Triggered Analog-Digital Conversion for Low-Power Wireless Sensor Nodes,” IEEE MWSCAS, Tempe, AZ, Aug 6-9, 2023 |
| 4) | Bhattacharyya S, Mathews P, Ayyappan PR, & Hasler J, “Toward Biorealistic Silicon Neural Circuits on Reconfigurable Platforms,” IEEE MWSCAS, Tempe, AZ, Aug 6-9, 2023 |
Skills
Experienced at several levels of semiconductor development.
Hardware Skills
| Area | Technologies |
|---|---|
| Mixed-Signal Design & Layout | 28 nm, 180 nm, 350 nm technologies |
| EEPROM (FG) Design, Programming, & Characterization | 65 nm (room temperature and cryogenic conditions) |
| Automated Test & Measurement | Analog Post-Si Verification |
| PCB Schematic Design and Layout | IPC Class II |
| FPGA Programming | |
| Signal Processing | |
| Semiconductor Physics | |
| Circuit Macromodels |
Software Skills
| Software/Tools | Description |
|---|---|
| Cadence Virtuoso | Layout, DRC, LVS tools |
| Cadence Spectre & Spice | |
| MATLAB | |
| Python | |
| C | Console & Embedded Applications |
| Altium Designer & KiCad | PCB Design Suite |
| Linux Environments |