Hello, I'm

Swagat Bhattacharyya

Field Applications Engineer · Renesas Electronics America

Neuromorphic circuits · Bioinspired computing · Analog/mixed-signal systems

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Swagat Bhattacharyya

Engineer. Researcher. Creative.

Valley landscape

Photo Credit: Sophia Asta

About Me

Background

You can call me Swag! My journey has taken me through three unique "West" locations: West Bengal, West Virginia, and West Lafayette. Although I've spent countless hours as a lab rat, I like to think I'm a bit different from the usual, having extensive industrial experience. With a vibrant and fun-loving personality, I've always been driven by a deep passion for learning and exploration, instilled in me by incredible teachers and mentors back in my enchanting hometown of Morgantown, West Virginia.

My academic adventures led me to Purdue University, where I triple majored in Electrical Engineering, Applied Physics, and Mathematics. I then joined Georgia Tech as an NSF Graduate Research Fellow and completed an MS in Electrical Engineering — my thesis focused on neuromorphic circuits and systems. I am currently a Field Applications Engineer at Renesas Electronics America. Outside of work, I find joy in working out with friends, reading, and practicing Hindustani classical music (vocal and bamboo flute).

Academic History

Institution Degree Year
Georgia Institute of Technology MS in Electrical Engineering 2024
Purdue University — Honors College BS in Electrical Engineering 2022
BS in Applied Physics 2022
BS in Mathematics 2022
Morgantown High School HS Diploma 2018

Research

My research is highly interdisciplinary, combining circuits, signal processing, controls, and computational neuroscience. I aim to create systems that can efficiently sense and process information like humans by utilizing bioinspired, asynchronous sensing and computing. An updated list of published works is on Google Scholar.

Patents

  1. Irazoqui P, Shah J, Meyer T, Ganesh V, Bhattacharyya S, & Hsiung Y, “Multimodal Seizure Sensing,” Published Nov 2023

Journal Articles

  1. Bhattacharyya S, “Performance Bounds for a Maxima-Sampling Envelope Detector,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol 72, no 10, Oct 2025
  2. Bhattacharyya S & Hasler J, “A Six-Transistor Integrate-and-Fire Neuron Enabling Chaotic Dynamics,” IEEE Transactions on Biomedical Circuits and Systems, vol 19, no 5, Oct 2025
  3. Kurup S, Bhattacharyya S, Banner RK, Yue K, Ayyappan PR, Aziz D, Elly HN, Barton KL, Hasler J, Filler MA, & Vogel EM, “Modular HfOx-RRAM for On-Demand Micromodular Electronics,” IEEE Electron Device Letters, vol 46, no 7, July 2025
  4. Mathews P, Ayyappan PR, Ige A, Bhattacharyya S, Yang L, & Hasler J, “A 65 nm CMOS Analog Programmable Standard Cell Library for Mixed-Signal Computing,” IEEE Transactions on VLSI Systems, vol 32, no 10, Oct 2024
  5. Bhattacharyya S & Hasler J, “Extrema-Triggered Conversion for Non-Stationary Signal Acquisition in Wireless Sensor Nodes,” JLPEA, vol 14, no 1, Feb 2024
  6. Bhattacharyya S, Ayyappan PR, & Hasler J, “Towards Scalable Digital Modeling of Networks of Biorealistic Silicon Neurons,” IEEE Journal on Emerging and Selected Topics in CAS, vol 13, no 4, pp 927–939, Dec 2023
  7. Bhattacharyya S & Graham DW, “Amplitude-Regulated Quadrature Sine-VCO Employing an OTA-C Topology,” IEEE Transactions on CAS II: Express Briefs, vol 70, no 6, pp 1886–1890, June 2023
  8. Bhattacharyya S, Andryzcik S, & Graham DW, “An Acoustic Vehicle Detector & Classifier Using a Reconfigurable Analog/Mixed-Signal Platform,” JLPEA, vol 10, no 1, Article 6, March–April 2020

Conference Papers

  1. Mathews P, Ayyappan PR, Ige A, Bhattacharyya S, Yang L, & Hasler J, “A 65nm and 130nm CMOS programmable analog standard cell library for scalable system synthesis,” IEEE CICC, Denver, CO, Apr 21–24, 2024
  2. Bhattacharyya S, Yang L, & Hasler J, “BuzzSort: A Linear-Time, Event-Driven Data Conversion and Sorting Framework for Approximate Computing Architectures,” IEEE ICRC, San Diego, CA, Dec 5–6, 2023
  3. Bhattacharyya S & Hasler J, “Extrema-Triggered Analog-Digital Conversion for Low-Power Wireless Sensor Nodes,” IEEE MWSCAS, Tempe, AZ, Aug 6–9, 2023
  4. Bhattacharyya S, Mathews P, Ayyappan PR, & Hasler J, “Toward Biorealistic Silicon Neural Circuits on Reconfigurable Platforms,” IEEE MWSCAS, Tempe, AZ, Aug 6–9, 2023
Buffalo landscape

Photo Credit: Sophia Asta

Skills

Experienced at several levels of semiconductor development.

Hardware

AreaTechnologies
Mixed-Signal Design & Layout28 nm, 180 nm, 350 nm technologies
EEPROM (FG) Design, Programming, & Characterization65 nm (room temperature and cryogenic conditions)
Automated Test & MeasurementAnalog Post-Si Verification
PCB Schematic Design and LayoutIPC Class II
FPGA Programming—
Signal Processing—
Semiconductor Physics—
Circuit Macromodels—

Software

ToolDescription
Cadence VirtuosoLayout, DRC, LVS tools
Cadence Spectre & Spice—
MATLAB—
Python—
CConsole & Embedded Applications
Altium Designer & KiCadPCB Design Suite
Linux Environments—